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21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 1 2109876543212109876543210987654321098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 PI74LVTC245 3.3V 8-Bit Bi-Directional Transceiver with 3-State Outputs Product Features * Advanced low power CMOS design for 2.7V to 3.6V VCC operation * Supports 5V input/output tolerance in mixed signal mode operation * Function compatible with LVT family of products * Balanced 24mA output drive * Typical VOLP (Output Ground Bounce) <0.8V at VCC=3.3V, TA=25C * Ioff and Power Up/Down 3-State support live insertion * Latch-up performance exceeds 200mA Per JESD78 * ESD protection exceeds JESD 22 - 2000V Human-Body Model (A114-B) - 200V Machine Model (A115-A) * Packages (Pb-free available): - 20-pin 209-mil wide plastic SSOP (H) - 20-pin 173-mil wide plastic TSSOP (L) 20-pin 300-mil wide plastic SOIC (S) Product Description Pericom Semiconductor's PI74LVTC series of logic circuits are produced using the Company's advanced CMOS technology, achieving industry leading speed. The PI74LVTC245 is a non-inverting 8-bit Bidirectional Transceiver designed for low-voltage 2.7V to 3.6V VCC operation, with the capability of interfacing to the 5V system environment. This tranceiver is designed for asynchronous two-way communication between data buses. The direction control input pin (DIR) determines the direction of the dataflow from the A bus to the B bus or from the B bus to the A bus. The output enable (OE) input, when HIGH, disables both A and B ports by placing them in HIGH Z condition. When Vcc is between 0 to 1.5V during power up or power down, the outputs of the device are in the high-impedance state. To ensure the high-impedance state above 1.5V, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current sinking capability of the driver. The device fully supports live-insertion with its Ioff and power-up/ down 3-state. The Ioff circuitry disables the outputs when the power is off, preventing the backflow of damaging current through the device. Power-up/down 3-state places the outputs in the high-impedance state during power up or power down, preventing driver conflict. Logic Block Diagram DIR OE A0 B0 A1 B1 A2 B2 A3 B3 A4 B4 A5 B5 A6 B6 A7 B7 Product Pin Configuration DIR A0 A1 A2 A3 A4 A5 A6 A7 GND 1 2 3 4 5 6 7 8 9 10 20 19 18 17 VCC OE B0 B1 B2 B3 B4 B5 B6 B7 20-Pin 16 H, L, S 15 14 13 12 11 1 PS8691 07/01/03 Truth Table(4) Inputs OE L L H Notes: 4. H = High Signal Level L = Low Signal Level X = Don't Care or Irrelevant Z = High Impedance 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 PI74LVTC245 3.3V, 8-Bit Bi-Directional Tranceiver with 3-State Outputs Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Supply voltage range, VCC ............................... -0.5V to +6.5V Input voltage range, VI(1) ................................. -0.5V to +6.5V Voltage range applied to any output in the high-impedance or power-off state, VO(1) ........ -0.5V to +6.5V Voltage range applied to any output in the active state, VO(1),(2) ................................. -0.5V to VCC +0.5V Input clamp current, IIK (VI <0) ..................................... -50mA Output clamp current, IOK (VO <0) ............................... -50mA Continous Output Current IO ....................................... 50mA Continous Current through each VCC or GND pin ............... 100mA Package thermal impedance, JA(3):package H ............ 81C/W package L ............. 84C/W package S ............. 84C/W Storage Temperature range, Tstg ..................... -65C to 150C Notes: Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 1. Input negative-voltage and output voltage ratings may be exceeded if the input and output clamp current ratings are observed. 2. This value is limited to 6.5 maximum 3. The package thermal impedance is calculated in accordance with JESD 51. Product Pin Description Pin Name OE DIR xAx xBx GND VCC De s cription 3- State Output Enable Inputs (Active LOW) Direction Control Input Side A Inputs or 3- State Outputs Side B Inputs or 3- State Outputs Ground Power Outputs DIR L H X Bus B Data to Bus A Bus A Data to Bus B Z 2 PS8691 07/01/03 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 PI74LVTC245 3.3V, 8-Bit Bi-Directional Tranceiver with 3-State Outputs Recommended Operating Conditions(5) M in. VC C VIH VIL VI VO Supply Voltage High- level Input Voltage Low- level Input Voltage Input Voltage Output Voltage High or Low State 3- State VC C = 2.7V VC C = 3.0V to 3.6V VC C = 2.7V VC C = 3.0V to 3.6V Operating VC C = 2.7V to 3.6V VC C = 2.7V to 3.6V 0 0 0 2.7 2.0 0.8 5.5 VC C 5.5 - 12 - 24 12 24 6 150 - 40 85 ns/V s/V C mA V M a x. 3.6 Units IO H High- level output current IO L Low- level output current t/V Input transition rise or fall rate t/VC C Power- up ramp rate TA Operating free- air temperature Notes: 5. All unused inputs must be held at VCC or GND to ensure proper device operation. 3 PS8691 07/01/03 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 PI74LVTC245 3.3V, 8-Bit Bi-Directional Tranceiver with 3-State Outputs DC Electrical Characteristics (Over the Operating Range, TA = -40C to +85C) Parame te rs VIK De s cription Clamp Diode Voltage VCC = 2.7V VCC = 2.7V VCC = 3V Te s t Conditions II = -18mA VCC -0.2V 2.2 2.4 2.2 0 .2 0.4 0.4 0.55 5 V IOH = -12mA IOH = -12mA IOH = -24mA M in. M a x. -1.2V Units VCC = 2.7V to 3.6V IOH = -100A VOH Output High Voltage VCC = 2.7V to 3.6V IOL = 100A VOL Output Low Voltage VCC = 2.7V VCC = 3V Control Inputs A or B Ports (6) VCC = 0V to 3.6V IOL = 12mA IOL = 12mA IOL = 24mA VI = 0V to 5.5V VI = 5.5V VCC = 3.6V VI = VCC VI = GND IOFF IOZPU IOZPD ICC ICC Power Off Output Leakage Current Power- Up 3- State Current Power- Down 3- State Current Quiescent Power Supply Current Increase in ICC VCC = 0V VCC = 0V to 1.5V VCC = 1.5V to 0V VCC = 2.7V to 3.6V VCC = 3.0V to 3.6V VI or VO = 0V to 5.5V VO = 0.5V to 5.5V, OE = don't care VO = 0.5V to 5.5V, OE = don't care VI = VCC or GND 3.6V VI 5.5V(7) IO = 0 II Input Leakage Current 5 5 A 5 5 100 500 One input at VCC - 0.6V(8), Other inputs at VCC or GND Notes: 6. For I/O ports, Input Leakage Current (II) includes the 3-state Output Leakage Current. Unused pins are at VCC or GND. 7. This applies in the disabled state only. 8. This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND. 4 PS8691 07/01/03 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 PI74LVTC245 3.3V, 8-Bit Bi-Directional Tranceiver with 3-State Outputs Capacitance Parame te rs CIN CIO C PD De s cription Control Input Capacitance Input/Output Capacitance Power Dissipation Capacitance (10) Te s t Conditions VCC = 3.3V, VI = VCC or GND VCC = 3.3V, VO = VCC or GND VCC = 3.3V, VI = 0 or VCC, f =10 MHz Typ.(9) 3.3 7.8 33 pF Units Notes: 9. All typical values are measured at VCC = 3.3V, TA = 25C. 10. CPD is defined as the value of the internal equivalent capacitance withic is derived from dynamic operating current consumption (ICCD) at no output loading and operating at 50% duty cycle, CPD is related to ICCD dynamic operating current by the expression: ICCD = (CPD)(VCC)(fIN)+(ICCstatic). Switching Characteristics Over Operating Range VCC = 3.3V 0.3V Parame te rs De s cription From (Input) To (Output) CL = 50pF, RL = 500Ohm M in tPLH tPHL tPZH tPZL tPHZ tPLZ tSK(O) Propagation Delay A or B B or A 1. 0 1.0 1. 0 1.0 1.0 1.0 M a x. 5.4 5.4 7.0 7.0 5.4 5.4 0.5 VCC = 2.7V CL = 50pF, RL = 500Ohm M in. 1.0 1.0 1.0 1.0 1.0 1.0 M a x. 5.8 5.8 7.9 7.9 5.8 5.8 ns Units Output Enable Time OE A or B Output Disable Time Output to Output Skew(11) OE A or B Notes: 11.Skew between any two outputs, switching in the same direction. 5 PS8691 07/01/03 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 PI74LVTC245 3.3V, 8-Bit Bi-Directional Tranceiver with 3-State Outputs PARAMETER MEASUREMENT INFORMATION VCC = 2.7V and 3.3V 0.3V 6V From Output Under Test CL = 50pF (See Note A) 500ohm S1 Open GND Te s t tPLH/tPHL tPLZ/tPZL tPHZ/tPZH S1 Open 6V GND 500ohm Load Circuit tW 2.7V Input 1.5V 1.5V 0V Voltage Waveforms Pulse Duration Output Control (Low Level Enabling) 2.7V 1.5V tPZL 1.5V VOL +0.3V tPHZ 1.5V VOH -0.3V VOH 0V VOL 1.5V 0V tPLZ 3V 2.7V Input 1.5V tPLH 1.5V Output 1.5V 0V tPHL VOH 1.5V VOL Output Waveform 1 S1 at 6V (see Note B) t PZH Output Waveform 2 S1 at GND (see Note B) Voltage Waveforms Propagation Delay Times Voltage Waveforms Enable and Disable Times Figure 1. Load Circuit and Voltage Waveforms Notes: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input impulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50ohm, tR 2.5ns, tF 2.5ns. D. The outputs are measured one at a time with one transition per measurement. 6 PS8691 07/01/03 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 PI74LVTC245 3.3V, 8-Bit Bi-Directional Tranceiver with 3-State Outputs Packaging Mechanical: 20-pin SSOP (H) 20 .197 .220 5.00 5.60 1 .272 .295 6.90 7.50 .078 2.00 Max SEATING PLANE .002 Min 0.050 .004 .009 0.09 0.25 0.55 .022 0.95 .037 .291 .322 7.40 8.20 .0256 BSC 0.65 .0098 Max. 0.25 X.XX DENOTES DIMENSIONS X.XX IN MILLIMETERS Packaging Mechanical: 20-pin TSSOP (L) 20 .169 .177 4.3 4.5 1 .252 .260 6.4 6.6 .004 0.09 .008 0.20 .047 1.20 Max 0.45 0.75 .018 .030 SEATING PLANE .238 .269 6.1 6.7 .0256 BSC 0.65 .007 .012 0.19 0.30 .002 0.05 .006 0.15 X.XX X.XX DENOTES CONTROLLING DIMENSIONS IN MILLIMETERS 7 PS8691 07/01/03 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 PI74LVTC245 3.3V, 8-Bit Bi-Directional Tranceiver with 3-State Outputs Packaging Mechanical: 20-pin SOIC (S) 20 .2914 .2992 7.40 7.60 .010 .029 0.254 x 45 0.737 1 .496 12.60 .511 12.99 .0091 .0125 0.41 .016 1.27 .050 .0926 .1043 2.35 2.65 SEATING PLANE .394 .419 10.00 10.65 0.23 0.32 0-8 .020 0.508 REF .030 0.762 .050 BSC 1.27 .013 .020 0.33 0.51 .0040 .0118 0.10 0.30 X.XX DENOTES CONTROLLING X.XX DIMENSIONS IN MILLIMETERS Ordering Information Orde ring Data PI74LVTC245H PI74LVTC245L PI74LVTC245S De s cription 20- pin, 209- mil wide plastic SSOP 20- pin, 173- mil wide plastic TSSOP 20- pin, 300- mil wide plastic SOIC Notes: 1. Thermal characteristics can be found on the company web site at http://www.pericom.com/packaging/mechanicals.php Pericom Semiconductor Corporation 2380 Bering Drive * San Jose, CA 95131 * 1-800-435-2336 * Fax (408) 435-1100 * http://www.pericom.com 8 PS8691 07/01/03 |
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